formal-verification
Formal property verification and model checking skill for FPGA designs
Best use case
formal-verification is best used when you need a repeatable AI agent workflow instead of a one-off prompt.
Formal property verification and model checking skill for FPGA designs
Teams using formal-verification should expect a more consistent output, faster repeated execution, less prompt rewriting.
When to use this skill
- You want a reusable workflow that can be run more than once with consistent structure.
When not to use this skill
- You only need a quick one-off answer and do not need a reusable workflow.
- You cannot install or maintain the underlying files, dependencies, or repository context.
Installation
Claude Code / Cursor / Codex
Manual Installation
- Download SKILL.md from GitHub
- Place it in
.claude/skills/formal-verification/SKILL.mdinside your project - Restart your AI agent — it will auto-discover the skill
How formal-verification Compares
| Feature / Agent | formal-verification | Standard Approach |
|---|---|---|
| Platform Support | Not specified | Limited / Varies |
| Context Awareness | High | Baseline |
| Installation Complexity | Unknown | N/A |
Frequently Asked Questions
What does this skill do?
Formal property verification and model checking skill for FPGA designs
Where can I find the source code?
You can find the source code on GitHub using the link provided at the top of the page.
SKILL.md Source
# Formal Verification Skill ## Overview Expert skill for formal property verification and model checking, enabling exhaustive verification of FPGA design properties without simulation. ## Capabilities - Write properties for formal verification - Configure formal tool constraints - Analyze formal counterexamples - Apply bounded model checking - Configure cover and assume directives - Debug formal failures - Integrate formal with simulation flows - Support JasperGold and VC Formal flows ## Target Processes - sva-development.js - cdc-design.js - constrained-random-verification.js ## Usage Guidelines ### Property Types - **assert property**: Must always hold - **assume property**: Environment constraints - **cover property**: Reachability goals - **restrict property**: Strong constraints ### Formal Approaches - **Bounded Model Checking**: Check properties up to N cycles - **Unbounded Proof**: Complete verification when possible - **Induction**: K-induction for liveness properties - **Abstraction**: Reduce complexity for scalability ### Writing Effective Properties ```systemverilog // Safety property assert property (@(posedge clk) disable iff (rst) req |-> ##[1:5] gnt); // Liveness property (bounded) assert property (@(posedge clk) disable iff (rst) req |-> s_eventually gnt); // Assumption for formal assume property (@(posedge clk) $onehot0(req_vec)); ``` ### Constraint Development - Model input protocol constraints - Constrain unrealistic scenarios - Avoid over-constraining - Use helper logic for complex constraints - Document constraint rationale ### Counterexample Analysis - Load counterexample trace - Identify root cause - Distinguish bug vs. missing constraint - Create regression test from counterexample - Update constraints or fix RTL ### Tool Integration - Configure engine selection - Set proof bounds appropriately - Use proof acceleration techniques - Integrate with regression flows - Archive proof results ## Dependencies - Formal tool awareness (JasperGold, VC Formal) - SVA expertise - Model checking theory knowledge
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